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| d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1995 mar 20 integrated circuits philips semiconductors TDA8761 9-bit analog-to-digital converter for digital video
1995 mar 20 2 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 features 9-bit resolution sampling rate up to 30 mhz dc sampling allowed one clock cycle conversion only high signal-to-noise ratio over a large analog input frequency range (8.5 effective bits at 10 mhz full-scale input at f clk = 30 mhz) no missing codes guaranteed in range (ir) 3-state ttl output ttl compatible digital inputs and outputs low-level ac clock input signal allowed external reference voltage regulator power dissipation only 360 mw (typical) low analog input capacitance, no buffer amplifier required no sample-and-hold circuit required. applications analog-to-digital conversion for: video data digitizing digital video broadcasting (dvb) cable tv. general description the TDA8761 is a 9-bit analog-to-digital converter (adc) for professional video and digital video set box applications. it converts the analog input signal into 9-bit binary-coded digital words at a maximum sampling rate of 30 mhz. its linearity performance ensures the required conversion accuracy in case of 256qam demodulator concept and for all symbol frequencies. all digital inputs and outputs are ttl compatible, although a low-level sine wave clock input signal is allowed. quick reference data note 1. f i = 11 mhz and f clk = 30 mhz; f i = 8 mhz and f clk = 20 mhz. ordering information symbol parameter conditions min. typ. max. unit v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output stages supply voltage 4.4 5.0 5.25 v i cca analog supply current - 30 tbf ma i ccd digital supply current - 22 tbf ma i cco output stages supply current - 22 tbf ma ainl ac integral non-linearity note 1; full scale input sine wave - 0.75 tbf lsb note 1; 50% full scale input sine wave - 0.5 tbf lsb adnl ac differential non-linearity note 1; full scale input sine wave - 0.5 tbf lsb note 1; 50% full scale input sine wave - 0.3 tbf lsb f clk(max) maximum clock frequency 30 -- mhz p tot total power dissipation - 360 tbf mw type number package name description version TDA8761m ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 1995 mar 20 3 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 block diagram fig.1 block diagram. handbook, full pagewidth 12 dgnd 5 6 8 7 9 agnd2 v rb v rm v rt v i 11 v ccd 3 26 v cca 21 22 23 24 20 d3 d4 d5 d6 d7 19 18 25 2 d2 d1 17 d0 d8 in range latch ttl outputs latches analog -to - digital converter clock driver mgc355 ttl output 1 clk 10 ce tc TDA8761 13 v cco1 4 agnd1 analog grounds digital ground 27 ognd2 14 ognd1 output grounds analog voltage input data outputs lsb msb 28 v cco2 ir output 1995 mar 20 4 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 pinning symbol pin description clk 1 clock input tc 2 twos complement input (active low) v cca 3 analog supply voltage (+5 v) agnd1 4 analog ground 1 agnd2 5 analog ground 2 v rb 6 reference voltage bottom input v rm 7 reference voltage middle v i 8 analog input voltage v rt 9 reference voltage top input ce 10 chip enable input (ttl level input, active low) v ccd 11 digital supply voltage (+5 v) dgnd 12 digital ground v cco1 13 supply voltage for output stages 1 (+5 v) ognd1 14 output ground 1 n.c. 15 not connected n.c. 16 not connected d0 17 data output; bit 0 (lsb) d1 18 data output; bit 1 d2 19 data output; bit 2 d3 20 data output; bit 3 d4 21 data output; bit 4 d5 22 data output; bit 5 d6 23 data output; bit 6 d7 24 data output; bit 7 d8 25 data output; bit 8 (msb) ir 26 in range data output ognd2 27 output ground 2 v cco2 28 supply voltage for output stages 2 (+5 v) fig.2 pin configuration. handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 clk tc cca agnd1 agnd2 rb rm i rt ce ccd dgnd cco1 ognd1 cco2 ognd2 ir d8 d7 d6 d5 d4 d3 d2 d1 d0 n.c. n.c. v v v v v v v v TDA8761 mgc356 1995 mar 20 5 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. the supply voltages v cca , v ccd and v cco may have any value between - 0.3 v and +7.0 v provided the difference between v cca , v ccd and v cco is between - 1 and +1 v. handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal characteristics symbol parameter conditions min. max. unit v cca analog supply voltage note 1 - 0.3 +7.0 v v ccd digital supply voltage note 1 - 0.3 +7.0 v v cco output stages supply voltage note 1 - 0.3 +7.0 v d v cc supply voltage differences between v cca and v ccd - 1.0 +1.0 v v cco and v ccd - 1.0 +1.0 v v cca and v cco - 1.0 +1.0 v v i input voltage referenced to agnd - 0.3 +7.0 v v i(p-p) ac input voltage for switching (peak-to-peak value) referenced to dgnd - v ccd v i o output current - 10 ma t stg storage temperature - 55 +150 c t amb operating ambient temperature 0 +70 c t j junction temperature - +150 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 110 k/w 1995 mar 20 6 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 characteristics v cca =v 3 to v 4 and v 5 = 4.75 to 5.25 v; v ccd =v 11 to v 12 = 4.75 to 5.25 v; v cco =v 13 and v 28 to v 14 and v 27 = 4.4 to 5.25 v; agnd and dgnd shorted together; t amb = 0 to +70 c; typical values measured at v cca =v ccd =v cco =5v; v i(p-p) = 1.5 v; c l = 15 pf and t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output stages supply voltage 4.4 5.0 5.25 v d v cc supply voltage differences between v cca and v ccd - 0.25 - +0.25 v v cca and v cco - 0.4 - +0.4 v v ccd and v cco - 0.4 - +0.4 v i cca analog supply current - 30 tbf ma i ccd digital supply current - 22 tbf ma i cco output stages supply current - 22 tbf ma inputs c lock input clk ( referenced to dgnd); note 1 v il low level input voltage 0 - 0.8 v v ih high level input voltage 2.0 - v ccd v i il low level input current v clk = 0.4 v - 10 +1 m a i ih high level input current v clk = 2.7 v -- 20 m a z i input impedance f clk =30mhz - 2 - k w c i input capacitance f clk =30mhz - 2 - pf i nput ce ( referenced to dgnd); see table 2 v il low level input voltage 0 - 0.8 v v ih high level input voltage 2.0 - v ccd v i il low level input current v il = 0.4 v - 400 -- m a i ih high level input current v ih = 2.7 v -- 20 m a v i ( analog input voltage referenced to agnd) i il low level input current v i = 1.3 v - 0 -m a i ih high level input current v i = 3.8 v - 70 -m a z i input impedance f i =10mhz - 5 - k w c i input capacitance f i =10mhz - 8 - pf 1995 mar 20 7 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 reference voltages for the resistor ladder; see table 1 v rb reference voltage bottom 1.2 1.3 - v v rt reference voltage top - 3.3 v cca - 0.8 v v v diff differential reference voltage v rt - v rb 1.8 2.0 3.0 v i ref reference current - 30 - ma r lad resistor ladder - 85 -w tc rlad temperature coef?cient of the resistor ladder - 1.86 - ppm - 158 - m w /k v osb offset voltage bottom note 2 - 250 - mv v ost offset voltage top note 2 - 250 - mv v i(p-p) analog input voltage (peak-to-peak value) note 3 1.3 1.5 2.5 v outputs d igital outputs d8 to d0 and ir ( referenced to ognd) v ol low level output voltage i o = 1 ma 0 - 0.4 v v oh high level output voltage i o = 0 ma 2.7 - v cco - 0.5 v i o = - 0.4 ma 2.7 - v cco - 1.3 v i o = - 1 ma 2.4 - v cco - 1.4 v i oz output current in 3-state mode 0.4 v < v o 1995 mar 20 9 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 notes 1. in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 2. analog input voltages producing code 0 up to and including code 511: a) v osb (voltage offset bottom) is the difference between the analog input which produces data equal to 00 and the reference voltage bottom (v rb ) at t amb =25 c. b) v ost (voltage offset top) is the difference between v rt (reference voltage top) and the analog input which produces data outputs equal to code 511 at t amb =25 c. 3. analog input voltage range can be derived from v rt - v rb difference. it is 4. 5. f i = 11 mhz and f clk = 30 mhz; f i = 8 mhz and f clk = 20 mhz. 6. the analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. no glitches greater than 2 lsbs, neither any significant attenuation are observed in the reconstructed signal. 7. the analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 8. effective bits are obtained via a fast fourier transform (fft) treatment taking 8k acquisition points per equivalent fundamental period. the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conversion to signal-to-noise ratio: s/n = eb 6.02 + 1.76 db. 9. intermodulation measured relative to either tone with analog input frequencies of 10.0 mhz and 10.10 mhz. the two input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter. 10. measurement carried out using video analyser vm700a, where the video analog signal is reconstructed through a digital-to-analog converter. 11. output data acquisition: the output data is available after the maximum delay time of t d . 3-state output delay times; see fig.4 t dzh enable high - tbf tbf ns t dzl enable low - tbf tbf ns t dhz disable high - tbf tbf ns t dlz disable low - tbf tbf ns symbol parameter conditions min. typ. max. unit v rt v rb C () 8 9 ------------------------------------------- ger v 511 v 0 C () 1.5 v C 1.5 v --------------------------------------------------- 100 = 1995 mar 20 10 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 table 1 output coding and input voltage (typical values; referenced to agnd, v rb = 1.3 v, v rt = 3.3 v) table 2 mode selection step v i(p-p) ir binary output bits twos complement output bits d8 d7 d6 d5 d4 d3 d2 d1 d0 d8 d7 d6 d5 d4 d3 d2 d1 d0 u/f < 1.55 0 0 00000000000000000 0 1.55 1 0 00000000000000000 1 . 1000000001000000001 . . ................... . . ................... 510 . 1111111111111111110 511 3.05 1 1 11111111111111111 o/f > 3.05 0 1 11111111111111111 tc ce d8 to d0 ir x 1 high impedance high impedance 0 0 active; twos complement active 1 0 active; binary active fig.3 timing diagram. handbook, full pagewidth ds t sample n + 1 sample n clk mgc357 sample n + 2 1.4 v v l data d0 to d8 t d t h cph t cpl t 2.4 v 0.4 v 1.4 v data n + 1 data n data n - 1 data n - 2 1995 mar 20 11 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 fig.4 timing diagram and test conditions of 3-state output delay time. f ce = 100 khz. handbook, full pagewidth mgc358 50 % 50 % high low dzh t dhz t 50 % high low dzl t dlz t 10 % 90 % output data v ccd output data 3.3 k w 15 pf s1 v ccd TDA8761 ce ce test dlz t dzl t dhz t dzh s1 ccd v ccd v gnd gnd t 1995 mar 20 12 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 fig.5 analog input settling-time diagram. handbook, full pagewidth mgc359 50 % stlh t 2 ns code 0 code 511 i 50 % 0.5 ns 50 % 2 ns sthl t 50 % 0.5 ns clk v fig.6 fast fourier transform (f clk = 30 mhz; f i = 10 mhz). effective bits: 8.58; thd = - 61.80 db. harmonic levels (db): 2nd = - 64.77; 3rd = - 79.30; 4th = - 71.90; 5th = - 66.12; 6th = - 82.29. handbook, full pagewidth 0 120 0 1.88 3.75 mgc360 40 80 9.37 5.63 7.50 11.3 13.1 15.0 f (mhz) 100 20 60 amplitude (db) 1995 mar 20 13 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 internal pin configurations fig.7 ttl data and in-range outputs. handbook, halfpage mgc361 ognd1 d8 to d0 o/uf v cco1 v cco2 fig.8 analog inputs. handbook, halfpage mgc040 agnd v cca v i fig.9 ce ( tc) 3-state input. n dbook, halfpage mgc041 ognd2 v cco1 (tc) ce fig.10 v rb , v rm and v rt . handbook, halfpage r mea050 agnd v rb v rm v cca v rt lad 1995 mar 20 14 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 fig.11 clk input. handbook, full pagewidth v v ccd clk dgnd mgc042 ref (1.3 v) 1995 mar 20 15 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 application information fig.12 application diagram. the analog and digital supplies should be separated and decoupled. the external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the lsb value. eventually, the reference ladder voltages can be derived from a well regulated v cca supply through a resistor bridge and a decoupled capacitor. for applications where the input signal must remain well centred around middle scale, v rm must be decoupled and connected to analog input signal (pin 8) through a resistor. the values must be defined in accordance with the input signal frequency in order to avoid direct coupling into the adc ladder (e.g. r = 5 k w and c = 100 nf). (1) v rb , v rm and v rt are decoupled to agnd. (2) pins 15 and 16 should be connected to dgnd in order to prevent noise influence. handbook, halfpage 28 27 26 25 24 23 22 21 20 19 18 17 TDA8761 ognd2 v cco1 d2 d3 d4 d5 d6 d7 d8 d1 d0 v ccd v cca 1 2 3 4 5 6 7 8 9 10 11 12 clk agnd1 agnd2 n.c. v rb v rm v rt mgc362 16 15 13 14 100 nf 100 nf dgnd ognd1 ir ce tc v cco2 agnd agnd 100 nf agnd v i (1) (1) (1) (2) n.c. (2) 1995 mar 20 16 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150ah 93-09-08 95-02-04 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2.0 1995 mar 20 17 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 soldering plastic small outline packages b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. r epairing soldered joints ( by hand - held soldering iron or pulse - heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. 1995 mar 20 18 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 notes 1995 mar 20 19 philips semiconductors preliminary speci?cation 9-bit analog-to-digital converter for digital video TDA8761 notes philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970), tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. (031)57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (9)0-50261, fax. (9)0-520971 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: p.o. box 10 63 23, 20043 hamburg, tel. (040)3296-0, fax. (040)3296 213. greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 hong kong: philips hong kong ltd., 15/f philips ind. bldg., 24-28 kung yip st., kwai chung, n.t., tel. (852)424 5121, fax. (852)480 6960/480 6009 india: philips india ltd, shivsagar estate, a block , dr. annie besant rd. worli, bombay 400 018 tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)7640 000, fax. (01)7640 200 italy: philips semiconductors s.r.l., piazza iv novembre 3, 20124 milano, tel. (0039)2 6752 2531, fax. (0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5028, fax. (03)3740 0580 korea: (republic of) philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)794-5011, fax. (02)798-8022 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb tel. (040)783749, fax. (040)788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546 philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd39 ? philips electronics n.v. 1995 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors printed in the netherlands 533061/1500/01/pp20 date of release: 1995 mar 20 document order number: 9397 750 00112 |
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